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preview ? 1 16, 32 meg x 64 ddr sdram dimms micron technology, inc., reserves the right to change products or specifications without notice. dd8c16_32x64ag_preview.p65 ? pub. 3/02 ?2002, micron technology, inc. 128mb (x64) 184-pin ddr sdram dimms ? this data sheet contains the present description of a product in definition with no formal design in progress. ddr sdram dimm module mt8vddt1664a - 128mb for the latest data sheet, please refer to the micron web site: www.micron.com/moduleds features ? 184-pin dual in-line memory module (dimm) fast data transfer rates pc 3200 utilizes 400 mt/s ddr sdram components 128mb (16 meg x 64) v dd = v dd q= +2.65v 0.10v v ddspd = +2.3v to +3.6v 2.5v i/o (sstl_2 compatible) commands entered on each positive ck edge dqs edge-aligned with data for reads; center- aligned with data for writes internal, pipelined double data rate (ddr) architec- ture; two data accesses per clock cycle bidirectional data strobe (dqs) transmitted/ received with data?i.e., source-synchronous data capture differential clock inputs (ck and ck#) four internal device banks for concurrent operation programmable burst lengths: 2, 4, or 8 auto precharge option auto refresh and self refresh modes 15.6s maximum average periodic refresh interval serial presence detect (spd) with eeprom programmable read cas latency gold-plated edge contacts address table 128mb refresh count 4k row addressing 4k (a0?a11) device bank addressing 4 (ba0, ba1) device configuration 16 meg x 8 column addressing 1k ( a0?a9) module bank addressing 1 ( s0#) part numbers and timing parameters part number part module configuration m odule me mory clock/ latency marking density bandwith data rate (cl - t rcd - t rp) mt8vddt1664ag-403_ -403 128mb 16 meg x 64 3.2 gb/s 5ns/400 mt/s 3-4-4 note : a ll part numbers end with a two-place code (not shown), designating component and pcb revisions. consult factory for current revision codes. example: mt8vddt1664ag-403 a1 options marking package unbuffered a 184-pin dimm (gold) g memory clock/speed, cas latency 5ns (200 mhz), 400 mt/s, cl = 3 -403 184-pin dimm mo-206
2 16, 32 meg x 64 ddr sdram dimms micron technology, inc., reserves the right to change products or specifications without notice. dd8c16_32x64ag_preview.p65 ? pub. 3/02 ?2002, micron technology, inc. 128mb (x64) 184-pin ddr sdram dimms preview pin symbol pin symbol pin symbol pin symbol 93 v ss 116 v ss 139 v ss 162 dq47 94 dq4 117 dq21 140 d n u 163 n c 95 dq5 118 a11 141 a10 164 v dd q 96 v dd q 119 dqs11/dm2 142 d n u 165 dq52 97 dqs9/dm0 120 v dd 143 v dd q 166 dq53 98 dq6 121 dq22 144 d n u 167 nc 99 dq7 122 a8 145 v ss 168 v dd 100 v ss 123 dq23 146 dq36 169 dqs15/dm6 101 n c 124 v ss 147 dq37 170 dq54 102 n c 125 a6 148 v dd 171 dq55 103 nc 126 dq28 149 dqs13/dm4 172 v dd 104 v dd q 127 dq29 150 dq38 173 n c 105 dq12 128 v dd q 151 dq39 174 dq60 106 dq13 129 dqs12/dm3 152 v ss 175 dq61 107 dqs10/dm1 130 a3 153 dq44 176 v ss 108 v dd 131 dq30 154 ras# 177 dqs16/dm7 109 dq14 132 v ss 155 dq45 178 dq62 110 dq15 133 dq31 156 v dd q 179 dq63 111 d n u 134 d n u 157 s0# 180 v dd q 112 v dd q 135 d n u 158 d n u 181 sa0 113 n c 136 v dd q 159 dqs14/dm5 182 sa1 114 dq20 137 ck0 160 v ss 183 sa2 115 nc 138 ck0# 161 dq46 184 v ddspd pin symbol pin symbol pin symbol pin symbol 1v ref 24 dq17 47 d n u 70 v dd 2 dq0 25 dqs2 48 a0 71 n c 3v ss 26 v ss 49 dnu 72 dq48 4 dq1 27 a9 50 v ss 73 dq49 5 dqs0 28 dq18 51 d n u 74 v ss 6 dq2 29 a7 52 b a 1 75 ck2# 7v dd 30 v dd q 53 dq32 76 ck2 8 dq3 31 dq19 54 v dd q77 v dd q 9nc 32 a5 55 dq33 78 dqs6 10 n c 33 dq24 56 dqs4 79 dq50 11 v ss 34 v ss 57 dq34 80 dq51 12 dq8 35 dq25 58 v ss 81 v ss 13 dq9 36 dqs3 59 ba0 82 n c 14 dqs1 37 a4 60 dq35 83 dq56 15 v dd q38 v dd 61 dq40 84 dq57 16 ck1 39 dq26 62 v dd q 85 v dd 17 ck1# 40 dq27 63 we# 86 dqs7 18 v ss 41 a2 64 dq41 87 dq58 19 dq10 42 v ss 65 cas# 88 dq59 20 dq11 43 a1 66 v ss 89 v ss 21 cke0 44 dnu 67 dqs5 90 nc 22 v dd q 45 dnu 68 dq42 91 sda 23 dq16 46 v dd 69 dq43 92 scl pin assignment (184-pin dimm f ront) pin assignment (184-pin dimm back) pin 93 pin 144 pin 145 pin 184 pin 1 pin 52 pin 53 pin 92 indicates a v dd or v dd q pin indicates a v ss pin no components this side of module back view front view u1 u2 u3 u4 u6 u7 u8 u9 u10
3 16, 32 meg x 64 ddr sdram dimms micron technology, inc., reserves the right to change products or specifications without notice. dd8c16_32x64ag_preview.p65 ? pub. 3/02 ?2002, micron technology, inc. 128mb (x64) 184-pin ddr sdram dimms preview pin descriptions pin numbers symbol type description 1v ref input sstl_2 reference voltage. 63, 65, 154 we#, cas#, input command inputs: ras#, cas#, and we# (along with ras# s0# and s1#) define the command being entered. 16, 17, 75, 76, 137, 138 ck0, ck0#, ck1, input clock: ck and ck# are differential clock inputs. all ck1#, ck2, ck2# address and control input signals are sampled on the crossing of the positive edge of ck and negative edge of ck#. output data (dq and dqs) is refer- enced to the crossings of ck and ck#. 21 cke0 input clock enable: cke high activates and cke low deactivates the internal clock, input buffers and output drivers. taking cke low provides precharge power-down and self refresh operations (all device banks idle), or active power-down (row active in any device bank). cke is synchronous for power-down entry and exit, and for self refresh entry. cke is asynchronous for self refresh exit and for disabling the outputs. cke must be maintained high throughout read and write accesses. input buffers (excluding ck, ck# and cke) are disabled during power-down. input buffers (excluding cke) are disabled during self refresh. cke is a sstl_2 input but will detect an lvcmos low level after v dd is applied. 157 s0# input chip select: s0# enables (registered low) and disables (registered high) the command decoder. all com- mands are masked when s0# is registered high. s0# is considered part of the command code. 52, 59 ba0, ba1 input bank address: ba0 and ba1 define to which device bank an active, read, write, or precharge command is being applied. 27, 29, 32, 37, 41, 43, 48, a0-a11 input address inputs: a0-a11 provide the row address for 118, 122, 125, 130, 141 active commands, and the column address and auto precharge bit (a10) for read/write commands, to select one location out of the memory array in the respective device bank. a10 sampled during a precharge command determines whether the precharge applies to one device bank (a10 low, device bank selected by ba0, ba1) or all device banks (a10 high). the address inputs also provide the op- code during a mode register set command. ba0 and ba1 define which mode register (mode register or extended mode register) is loaded during the load mode register command. 91 sda input/ serial presence-detect data: sda is a bidirectional pin output used to transfer addresses and data into and out of the presence-detect portion of the module. note: pin numbers may not correlate with symbols. refer to pin assignment tables for pin number and symbol information.
4 16, 32 meg x 64 ddr sdram dimms micron technology, inc., reserves the right to change products or specifications without notice. dd8c16_32x64ag_preview.p65 ? pub. 3/02 ?2002, micron technology, inc. 128mb (x64) 184-pin ddr sdram dimms preview pin descriptions (continued) pin numbers symbol type description 92 scl input serial clock for presence-detect: scl is used to synchronize the presence-detect data transfer to and from the module. 181, 182, 183 sa0-sa2 input presence-detect address inputs: these pins are used to configure the presence-detect device. 5, 14, 25, 36, 56, 67, 78, dqs0-dqs16 input/ data strobe: dqs0-dqs7, output with read data, input 86, 97, 107, 119, 129, output with write data. dqs is edge-aligned with read data, 149, 159, 169, 177 centered in write data. used to capture data. data mask: dqs9-dqs16 function as dm0-dm7 to mask write data when when high. 2, 4, 6, 8, 12, 13, 19, 20, dq0-dq63 input/ data i/os: data bus. 23, 24, 28, 31, 33, 35, 39, output 40, 53, 55, 57, 60, 61, 64, 68, 69, 72, 73, 79, 80, 83, 84, 87, 88, 94, 95, 98, 99, 105, 106, 109, 110, 114, 117, 121, 123, 126, 127, 131, 133, 146, 147, 150, 151, 153, 155, 161, 162, 165, 166, 170, 171, 174, 175, 178, 179 15, 22, 30, 54, 62, 77, 96, v ddq supply dq power supply: +2.65v +0.10v. 104, 112, 128, 136, 143, 156, 164, 172, 180 7, 38, 46, 70, 85, 108, v dd supply power supply: +2.65v +0.10v. 120, 148, 168 3, 11, 18, 26, 34, 42, 50, v ss supply ground. 58, 66, 74, 81, 89, 93, 100, 116, 124, 132, 139, 145, 152, 160, 176 184 v ddspd supply serial eeprom positive power supply, 2.3v to 3.6v. 9, 10, 71, 82, 90, 101, nc ? no connect: these pins should be left unconnected. 102, 103, 113, 115, 163, 167, 173 44, 45, 47, 49, 51, 111, dnu ? do not use: these pins are not connected on this 134, 135, 140, 142, 144, module but are assigned pins on other modules in 158 this product family. note: pin numbers may not correlate with symbols. refer to pin assignment tables for pin number and symbol information.
5 16, 32 meg x 64 ddr sdram dimms micron technology, inc., reserves the right to change products or specifications without notice. dd8c16_32x64ag_preview.p65 ? pub. 3/02 ?2002, micron technology, inc. 128mb (x64) 184-pin ddr sdram dimms preview functional block diagram a0 sa0 serial pd u10 sda a1 sa1 a2 sa2 ba0, ba1 a0-a11 (128mb) ras# cas# cke0 we# ba0, ba1: ddr sdrams a0-a11: ddr sdrams ras#: ddr sdrams cas#: ddr sdrams cke0: ddr sdrams we#: ddr sdrams v ref v ss ddr sdrams ddr sdrams dq56 dq57 dq58 dq59 dq60 dq61 dq62 dq63 u9 dq dq dq dq dq dq dq dq dq48 dq49 dq50 dq51 dq52 dq53 dq54 dq55 u7 dq dq dq dq dq dq dq dq dq40 dq41 dq42 dq43 dq44 dq45 dq46 dq47 u6 dq dq dq dq dq dq dq dq dq32 dq33 dq34 dq35 dq36 dq37 dq38 dq39 dq24 dq25 dq26 dq27 dq28 dq29 dq30 dq31 u4 dq dq dq dq dq dq dq dq dq16 dq17 dq18 dq19 dq20 dq21 dq22 dq23 u2 dq dq dq dq dq dq dq dq dq8 dq9 dq10 dq11 dq12 dq13 dq14 dq15 dm cs# dqs u1 dq dq dq dq dq dq dq dq dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 dqs9/dm0 ms0# u3 dq dq dq dq dq dq dq dq wp scl dm cs# dqs dm cs# dqs dm cs# dqs dqs0 dqs13/dm4 dqs4 dqs10/dm1 dqs1 dqs14/dm5 dqs5 dqs11/dm2 dqs2 dqs15/dm6 dqs6 dm cs# dqs u8 dq dq dq dq dq dq dq dq dm cs# dqs dm cs# dqs dm cs# dqs dqs12/dm3 dqs3 dqs16/dm7 dqs7 v ddq v dd ddr sdrams ddr sdrams ddr sdram x 2 ck0 ck0# 120 ddr sdram x 3 ck1 ck1# 120 ddr sdram x 3 ck2 ck2# 120 mt46v16m8tg = ddr sdrams, 128mb modules v ddspd spd note: 1. all resistor values are 22 ohms unless otherwise specified. 2. per industry standard, micron utilizes various component speed grades as referenced in the module part numbering guide at www.micron.com/numberguide . 3. to optimize system and loading and signal integrity for -403 speed grade modules, 3 ? (single bank modules) or 5 ? (dual bank modules) stub resistors may be placed on command/address and control lines. contact micron ccg applications for additional information.
6 16, 32 meg x 64 ddr sdram dimms micron technology, inc., reserves the right to change products or specifications without notice. dd8c16_32x64ag_preview.p65 ? pub. 3/02 ?2002, micron technology, inc. 128mb (x64) 184-pin ddr sdram dimms preview general description the mt8vddt1664a is a high-speed cmos, dy- namic random-access, 128mb memory module orga- nized in a x64 configuration. this module uses inter- nally configured quad-bank ddr sdram devices. this ddr sdram module uses a double data rate architecture to achieve high-speed operation. the double data rate architecture is essentially a 2 n - prefetch architecture with an interface designed to transfer two data words per clock cycle at the i/o pins. a single read or write access for the ddr sdram mod- ule effectively consists of a single 2 n -bit wide, one- clock-cycle data transfer at the internal dram core and two corresponding n -bit wide, one-half-clock-cycle data transfers at the i/o pins. a bidirectional data strobe (dqs) is transmitted ex- ternally, along with data, for use in data capture at the receiver. dqs is an intermittent strobe transmitted by the ddr sdram during reads and by the memory con- troller during writes. dqs is edge-aligned with data for reads and center-aligned with data for writes. this ddr sdram module operates from multiple differential clocks (ck and ck#); the crossing of ck go- ing high and ck# going low will be referred to as the positive edge of ck. commands (address and control signals) are registered at every positive edge of ck. in- put data is registered on both edges of dqs, and output data is referenced to both edges of dqs, as well as to both edges of ck. read and write accesses to the ddr sdram mod- ule is burst oriented; accesses start at a selected loca- tion and continue for a programmed number of loca- tions in a programmed sequence. accesses begin with the registration of an active command, which is then followed by a read or write command. the address bits registered coincident with the active command are used to select the device bank and row to be ac- cessed (ba0, ba1 select devices bank; a0-a11 select device row). the address bits registered coincident with the read or write command (a0-a9) are used to select the device bank and the starting device column location for the burst access. these ddr sdram modules provide for program- mable read or write burst lengths of 2, 4, or 8 loca- tions. an auto precharge function may be enabled to provide a self-timed row precharge that is initiated at the end of the burst access. the pipelined, multibank architecture of ddr sdram modules allows for concurrent operation, thereby providing high effective bandwidth by hiding row precharge and activation time. an auto refresh mode is provided, along with a power-saving power-down mode. all inputs are com- patible with the jedec standard for sstl_2. all out- puts are sstl_2, class ii compatible. for more infor- mation regarding ddr sdram operation, refer to the 128mb and 256mb ddr sdram data sheet. serial presence-detect operation these ddr sdram modules incorporate serial pres- ence-detect (spd). the spd function is implemented using a 2,048-bit eeprom. this nonvolatile storage device contains 256 bytes. the first 128 bytes can be programmed by micron to identify the module type and various sdram organizations and timing param- eters. the remaining 128 bytes of storage are available for use by the customer. system read/write opera- tions between the master (system logic) and the slave eeprom device (dimm) occur via a standard iic bus using the dimm?s scl (clock) and sda (data) signals, together with sa(2:0), which provide eight unique dimm/eeprom addresses. register definition mode register the mode register is used to define the specific mode of operation of the ddr sdram. this definition in- cludes the selection of a burst length, a burst type, a cas latency and an operating mode, as shown in the mode register diagram. the mode register is pro- grammed via the mode register set command (with ba0 = 0 and ba1 = 0) and will retain the stored informa- tion until it is programmed again or the device loses power (except for bit a8, which is self-clearing). reprogramming the mode register will not alter the contents of the memory, provided it is performed cor- rectly. the mode register must be loaded (reloaded) when all device banks are idle and no bursts are in progress, and the controller must wait the specified time before initiating the subsequent operation. vio- lating either of these requirements will result in un- specified operation. mode register bits a0-a2 specify the burst length, a3 specifies the type of burst (sequential or interleaved), a4- a6 specify the cas latency, and a7-a11 specify the operating mode. burst length read and write accesses to the ddr sdram are burst oriented, with the burst length being programmable, as shown in mode register diagram. the burst length determines the maximum number of column locations that can be accessed for a given read or write com- mand. burst lengths of 2, 4, or 8 locations are available for both the sequential and the interleaved burst types.
7 16, 32 meg x 64 ddr sdram dimms micron technology, inc., reserves the right to change products or specifications without notice. dd8c16_32x64ag_preview.p65 ? pub. 3/02 ?2002, micron technology, inc. 128mb (x64) 184-pin ddr sdram dimms preview reserved states should not be used, as unknown operation or incompatibility with future versions may result. when a read or write command is issued, a block of columns equal to the burst length is effectively selected. all accesses for that burst take place within this block, meaning that the burst will wrap within the block if a boundary is reached. the block is uniquely selected by a1-a11 when the burst length is set to two, by a2-a11 when the burst length is set to four and by a3-a11 when the burst length is set to eight (where a11 is the most significant column address bit for a given con- figuration). the remaining (least significant) address bit(s) is (are) used to select the starting location within the block. the programmed burst length applies to both read and write bursts. burst type accesses within a given burst may be programmed to be either sequential or interleaved; this is referred to as the burst type and is selected via bit m3. the ordering of accesses within a burst is deter- mined by the burst length, the burst type and the start- ing column address, as shown in burst definition table. burst definition table burst starting column order of accesses within a burst length address type = sequential type = interleaved a0 2 00-1 0-1 11-0 1-0 a1 a0 0 0 0-1-2-3 0-1-2-3 4 0 1 1-2-3-0 1-0-3-2 1 0 2-3-0-1 2-3-0-1 1 1 3-0-1-2 3-2-1-0 a2 a1 a0 0 0 0 0-1-2-3-4-5-6-7 0-1-2-3-4-5-6-7 0 0 1 1-2-3-4-5-6-7-0 1-0-3-2-5-4-7-6 0 1 0 2-3-4-5-6-7-0-1 2-3-0-1-6-7-4-5 8 0 1 1 3-4-5-6-7-0-1-2 3-2-1-0-7-6-5-4 1 0 0 4-5-6-7-0-1-2-3 4-5-6-7-0-1-2-3 1 0 1 5-6-7-0-1-2-3-4 5-4-7-6-1-0-3-2 1 1 0 6-7-0-1-2-3-4-5 6-7-4-5-2-3-0-1 1 1 1 7-0-1-2-3-4-5-6 7-6-5-4-3-2-1-0 note: 1. for a burst length of two, a1-a11 select the two- data-element block; a0 selects the first access within the block. 2. for a burst length of four, a2-a11 select the four- data-element block; a0-a1 select the first access within the block. 3. for a burst length of eight, a3-a11 select the eight-data-element block; a0-a2 select the first access within the block. 4. whenever a boundary of the block is reached within a given sequence above, the following access wraps within the block. mode register definition diagram m3 = 0 reserved 2 4 8 reserved reserved reserved reserved m3 = 1 reserved 2 4 8 reserved reserved reserved reserved operating mode normal operation normal operation/reset dll all other states reserved 0 1 - 0 0 - 0 0 - 0 0 - 0 0 - valid valid - 0 1 burst type sequential interleaved cas latency reserved reserved 2 3 reserved reserved reserved reserved burst length m0 0 1 0 1 0 1 0 1 burst length cas latency bt 0* a9 a7 a6 a5 a4 a3 a8 a2 a1 a0 mode register (mx) address bus 976543 8210 m1 0 0 1 1 0 0 1 1 m2 0 0 0 0 1 1 1 1 m3 m4 0 1 0 1 0 1 0 1 m5 0 0 1 1 0 0 1 1 m6 0 0 0 0 1 1 1 1 m6-m0 m8 m7 operating mode a10 ba0 a11 ba1 10 11 12 13 0* * m13 and m12 (ba0 and ba1) must be ? 0, 0 ? to select the base mode register (vs. the extended mode register). m9 m10 m11
8 16, 32 meg x 64 ddr sdram dimms micron technology, inc., reserves the right to change products or specifications without notice. dd8c16_32x64ag_preview.p65 ? pub. 3/02 ?2002, micron technology, inc. 128mb (x64) 184-pin ddr sdram dimms preview read latency the read latency is the delay, in clock cycles, be- tween the registration of a read command and the avail- ability of the first bit of output data. the latency should be set to 3 clocks, as shown in cas latency diagram and the mode register definition diagram. if a read command is registered at clock edge n , and the latency is m clocks, the data will be available nominally coincident with clock edge n + m . the cas latency table indicates the operating frequencies at which each cas latency setting can be used. reserved states should not be used as unknown op- eration or incompatibility with future versions may re- sult. ck ck# command dq dqs cl = 3 read nop nop nop burst length = 4 in the cases shown shown with nominal t ac and nominal t dsdq t0 t1 t2 t2n t3 t3n don ? t care transitioning data cas latency diagram allowable operating clock frequency (mhz) speed cl = 3 -403 200 cas latency (cl) table operating mode the normal operating mode is selected by issuing a mode register set command with bits a7-a11 (for the 128mb), or a7-a12 (for the 256mb module) each set to zero, and bits a0-a6 set to the desired values. a dll reset is initiated by issuing a mode register set command with bits a7 and a9-a11 (for 128mb mod- ule), or a7 and a9-a12 (for 256mb module) each set to zero, bit a8 set to one, and bits a0-a6 set to the desired values. although not required by the micron device, jedec specifications recommend when a load mode register command is issued to reset the dll, it should always be followed by a load mode regis- ter command to select normal operating mode. all other combinations of values for a7-a11, or a7- a12 are reserved for future use and/or test modes. test modes and reserved states should not be used be- cause unknown operation or incompatibility with fu- ture versions may result.
9 16, 32 meg x 64 ddr sdram dimms micron technology, inc., reserves the right to change products or specifications without notice. dd8c16_32x64ag_preview.p65 ? pub. 3/02 ?2002, micron technology, inc. 128mb (x64) 184-pin ddr sdram dimms preview extended mode register the extended mode register controls functions be- yond those controlled by the mode register; these addi- tional functions are dll enable/disable, output drive strength, and qfc#. these functions are controlled via the bits shown in the extended mode register defini- tion diagram. the extended mode register is pro- grammed via the load mode register command to the mode register (with ba0 = 1 and ba1 = 0) and will retain the stored information until it is programmed again or the device loses power. the enabling of the dll should always be followed by a load mode register command to the mode register (ba0/ba1 both low) to reset the dll. the extended mode register must be loaded when all device banks are idle and no bursts are in progress, and the controller must wait the specified time before initiat- ing any subsequent operation. violating either of these requirements could result in unspecified operation. output drive strength the normal full drive strength for all outputs is speci- fied to be sstl2, class ii. for detailed information on output drive strength option, refer to the 128mb ddr sdram data sheet. dll enable/disable the dll must be enabled for normal operation. dll enable is required during power-up initialization and upon returning to normal operation after having disabled the dll for the purpose of debug or evalua- tion. (when the device exits self refresh mode, the dll is enabled automatically.) any time the dll is enabled, 200 clock cycles must occur before a read command can be issued. extended mode register definition diagram operating mode reserved reserved 0 ? 0 ? valid ? 0 1 dll enable disable e0 0 drive strength normal e1 2 0 ? qfc# function disabled reserved e2 3 e0 e1, note: 1. e13 and e12 (ba1 and ba0) must be ? 0, 1 ? to select the extended mode register (vs. the base mode register). 2. the qfc# option is not supported. e2, e3 e4 0 ? 0 ? 0 ? 0 ? 0 ? e6 e5 e7 e8 e9 0 ? 0 ? e10 e11 0 ? e12 dll 1 1 0 1 a9 a7 a6 a5 a4 a3 a8 a2 a1 a0 extended mode register (ex) address bus 9 7 654 3 8 2 1 0 operating mode a10 a11 ba1 ba0 10 11 12 13 ds qfc
10 16, 32 meg x 64 ddr sdram dimms micron technology, inc., reserves the right to change products or specifications without notice. dd8c16_32x64ag_preview.p65 ? pub. 3/02 ?2002, micron technology, inc. 128mb (x64) 184-pin ddr sdram dimms preview note: 1. cke is high for all commands shown except self refresh. 2. ba0-ba1 select either the mode register or the extended mode register (ba0 = 0, ba1 = 0 select the mode register; ba0 = 1, ba1 = 0 select extended mode register; other combinations of ba0-ba1 are reserved). a0-a11 provide the op- code to be written to the selected mode register. 3. ba0-ba1 provide device bank address and a0-a11 provide device row address. 4. ba0-ba1 provide device bank address; a0-a9 provide device column address; a10 high enables the auto precharge feature (nonpersistent), and a10 low disables the auto precharge feature. 5. a10 low: ba0-ba1 determine which device bank is precharged. a10 high: all device banks are precharged and ba0- ba1 are ? don ? t care. ? 6. this command is auto refresh if cke is high, self refresh if cke is low. 7. internal refresh counter controls device row addressing; all inputs and i/os are ? don ? t care ? except for cke. 8. applies only to read bursts with auto precharge disabled; this command is undefined (and should not be used) for read bursts with auto precharge enabled and for write bursts. 9. deselect and nop are functionally interchangeable. 10. used to mask write data; provided coincident with the corresponding data. truth table ? commands (note: 1) name (function) cs# ras# cas# we# addr notes deselect (nop) h x x x x 9 no operation (nop) l h h h x 9 active (select bank and activate row) l l h h bank/row 3 read (select bank and column, and start read burst) l h l h bank/col 4 write (select bank and column, and start write burst) l h l l bank/col 4 burst terminate l h h l x 8 precharge (deactivate row in bank or banks) l l h l code 5 auto refresh or self refresh l l l h x 6, 7 (enter self refresh mode) load mode register llll op-code 2 truth table ? dm operation (note: 10) name (function) dm dq write enable l valid write inhibit hx commands the truth tables below provides a general reference of available commands. for a more detailed description of commands and operations, refer to the 128mb ddr sdram data sheet.
11 16, 32 meg x 64 ddr sdram dimms micron technology, inc., reserves the right to change products or specifications without notice. dd8c16_32x64ag_preview.p65 ? pub. 3/02 ?2002, micron technology, inc. 128mb (x64) 184-pin ddr sdram dimms preview absolute maximum ratings* voltage on v dd supply relative to v ss .............................................. -1v to +3.6v voltage on v dd q supply relative to v ss .............................................. -1v to +3.6v voltage on v ref and inputs relative to v ss .............................................. -1v to +3.6v voltage on i/o pins relative to v ss ................................. -0.5v to v dd q +0.5v operating temperature, t a (ambient) ........ 0c to +70c storage temperature (plastic) ................ -55c to +150c power dissipation .......................................................... 8w short circuit output current .................................. 50ma *stresses greater than those listed under ?absolute maxi- mum ratings? may cause permanent damage to the de- vice. this is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. dc electrical characteristics and operating conditions (refer to standard 128mb ddr sdram data sheet for full functionality and notes) (0 c t a +70 c; v dd = +2.65v 0.10v, v dd q = +2.65v 0.10v) parameter/condition symbol min max units supply voltage v dd 2.45 2.75 v i/o supply voltage v dd q 2.45 2.75 v i/o reference voltage v ref 0.49 x v dd q 0.51 x v dd qv i/o termination voltage (system) v tt v ref - 0.04 v ref + 0.04 v input high (logic 1) voltage v ih ( dc )v ref + 0.15 v dd + 0.3 v input low (logic 0) voltage v il ( dc ) -0.3 v ref - 0.15 v input leakage current command/ any input 0v v in v dd , v ref pin 0v v in 1.35v address, s0#, i i -16 16 a (all other pins not under test = 0v) cke0 ck1, ck1#, ck2,ck2# i i -6 6 a ck0, ck0# i i -4 4 a output leakage current (dqs are disabled; 0v v out v dd q) i oz -5 5 a output levels: high current (v out = v dd q-0.373v, minimum v ref , minimum v tt )i oh -16.8 ? ma low current (v out = 0.373v, maximum v ref , maximum v tt ) i ol 16.8 ? ma ac input operating conditions (refer to standard 128mb ddr sdram data sheet for full functionality and notes) (0 c t a +70 c; v dd = +2.65v 0.10v, v dd q = +2.65v 0.10v) parameter/condition symbol min max units input high (logic 1) voltage v ih ( ac )v ref + 0.310 ? v input low (logic 0) voltage v il ( ac ) ? v ref - 0.310 v i/o reference voltage v ref ( ac ) 0.49 x v dd q 0.51 x v dd qv
12 16, 32 meg x 64 ddr sdram dimms micron technology, inc., reserves the right to change products or specifications without notice. dd8c16_32x64ag_preview.p65 ? pub. 3/02 ?2002, micron technology, inc. 128mb (x64) 184-pin ddr sdram dimms preview * module ac timing parameters comply with pc3200 design specifications, based on ddr sdram component performance parameters. electrical characteristics and recommended ac operating conditions* (refer to standard 128mb ddr sdram data sheet for full functionality and notes) (0 c t a +70 c; v dd = +2.65v 0.10v, v dd q = +2.65v 0.10v) ac characteristics -403 parameter symbol min max units access window of dqs from ck/ck# t ac -0.60 + 0.60 ns ck high-level width t ch 0.45 0.55 t ck ck low-level width t cl 0.45 0.55 t ck clock cycle time cl = 3 t ck (3) 5 5 ns dq and dm input hold time relative to dqs t dh 0.45 ns dq and dm input setup time relative to dqs t ds 0.45 ns dq and dm input pulse width (for each input) t dipw 1.4 ns access window of dqs from ck/ck# t dqsck -0.50 + 0.50 ns dqs input high pulse width t dqsh 0.40 t ck dqs input low pulse width t dqsl 0.40 t ck dqs-dq skew, dqs to last dq valid, per group, per access t dqsq 0.35 ns write command to first dqs latching transition t dqss 0.75 1.25 t ck dqs falling edge to ck rising - setup time t dss 0.22 t ck dqs falling edge from ck rising - hold time t dsh 0.22 t ck half clock period t hp t ch, t cl ns data-out high-impedance window from ck/ck# t hz +0.60 ns data-out low-impedance window from ck/ck# t lz -0.60 ns address and control input hold time (fast slew rate) t ih f 0.75 ns address and control input setup time (fast slew rate) t is f 0.75 ns address and control input hold time (slow slew rate) t ih s na ns address and control input setup time (slow slew rate) t is s na ns load mode register command cycle time t mrd 10 ns dq-dqs hold, dqs to first dq to go non-valid, per access t qh t hp- t qhs ns data hold skew factor t qhs 0.50 ns active to precharge command t ras 40 70,000 ns active to read with auto precharge c ommand t rap 15 ns active to active/auto refresh command period t rc 60 ns auto refresh command period t rfc 70 ns active to read or write delay t rcd 20 ns precharge command period t rp 20 ns dqs read preamble t rpre 0.9 1.1 t ck dqs read postamble t rpst 0.4 0.6 t ck active bank a to active bank b command t rrd 10 ns dqs write preamble t wpre 0.25 t ck dqs write preamble setup time t wpres 0 ns dqs write postamble t wpst 0.4 0.6 t ck write recovery time t wr 15 ns internal write to read command delay t wtr 2 t ck
13 16, 32 meg x 64 ddr sdram dimms micron technology, inc., reserves the right to change products or specifications without notice. dd8c16_32x64ag_preview.p65 ? pub. 3/02 ?2002, micron technology, inc. 128mb (x64) 184-pin ddr sdram dimms preview electrical characteristics and recommended ac operating conditions* (refer to standard 128mb ddr sdram data sheet for full functionality and notes) (0 c t a +70 c; v dd = +2.65v 0.10v, v dd q = +2.65v 0.10v) ac characteristics -403 parameter symbol min max units data valid output window na t qh - t dqsq ns refresh to refresh command interval t refc 140.6 s average periodic refresh interval t refi 15.6 s terminating voltage delay to v dd t vtd 0 ns exit self refresh to non-read command t xsnr 75 ns exit self refresh to read command t xsrd 200 t ck capacitance (all modules) (refer to standard 128mb ddr sdram data sheet for full functionality and notes) parameter symbol min max units input/output capacitance: dq, dqs c io 4.0 5.0 p f input capacitance: command and address, s0# c i 1 16.0 24.0 p f input capacitance: ck0, ck0# c i 2 a 4.0 6.0 p f input capacitance: ck1, ck1#; ck2, ck2# c i 2 b 6.0 9.0 p f input capacitance: cke0 c i 3 16.0 24.0 p f * module ac timing parameters comply with pc3200 design specifications, based on ddr sdram component performance parameters.
14 16, 32 meg x 64 ddr sdram dimms micron technology, inc., reserves the right to change products or specifications without notice. dd8c16_32x64ag_preview.p65 ? pub. 3/02 ?2002, micron technology, inc. 128mb (x64) 184- pin ddr sdram dimms preview serial presence-detect matrix (note: 1) byte description entry (v ersion) mt8 vddt1664a 0 number of bytes used by micron 128 80 1 total number of spd memory bytes 256 08 2 memory type sdram ddr 07 3 number of row addresses 12 or 13 0c 4 number of column addresses 10 0a 5 number of banks 1 01 6 module data width 64 40 7 module data width (continued) 0 00 8 module voltage interface levels sstl 2.5v 04 9 sdram cycle time, t ck (cas latency = 3) 5ns 50 10 sdram access from clock, t ac (cas latency = 3) 0.60ns 60 11 module configuration type none 00 12 refresh rate/type 15.6s/self 80 13 sdram width (primary sdram) 8 08 14 error-checking sdram data width none 00 15 minimum clock delay, back-to-back 1 01 random column access 16 burst lengths supported 2, 4, 8 0e 17 number of banks on sdram device 4 04 18 cas latencies supported 2, 2.5 0c 19 cs latency 001 20 we latency 102 21 sdram module attributes diff. clk input 20 22 sdram device attributes: general fast / concurrent c0 auto precharge 23 sdram cycle time, t ck (cas latency = 2) ? 00 24 sdram cycle time, t ck (cas latency = 2) ? 00 25 sdram cycle time, t ck ? 00 (cas latency = 1) 26 sdram access from ck , t ac ? 00 (cas latency = 1) 27 minimum row precharge time, t rp 20ns 50 28 minimum row active to row active, t rrd 10ns 28 29 minimum ras# to cas# delay, t rcd 20ns 50 note: 1. ?1?/?0?: serial data, ?driven to high?/?driven to low.?
15 16, 32 meg x 64 ddr sdram dimms micron technology, inc., reserves the right to change products or specifications without notice. dd8c16_32x64ag_preview.p65 ? pub. 3/02 ?2002, micron technology, inc. 128mb (x64) 184-pin ddr sdram dimms preview serial presence-detect matrix (continued) (notes: 1, 2) byte description entry (v ersion) mt8 vddt1664a 30 minimum ras# pulse width, t ras 40ns 28 31 module bank density 128mb or 256mb 20 32 address and command setup time, t is 0.75ns 75 [value set to slow slew rate ( t is s )] (note 3) 33 address and command hold time, t ih 0.75ns 75 [value set to slow slew rate ( t ih s )] (note 3) 34 data/data mask input setup time, t ds 0.45ns 45 35 data/data mask input hold time, t dh 0.45ns 45 36-40 reserved 00 41 minimum active/auto refresh time, 60ns 3c 42 minimum auto refresh to active/auto refresh command period, 70ns 46 ( t rfc) 43 maximum cycle time, ( t ck (max)) 5ns 14 44 maximum dqs-dq skew time, ( t dqsq) 0.35ns 23 45 maximum read data hold skew 0.50ns 50 46-61 reserved 00 00 62 spd revision release 0.0 00 63 checksum for bytes 0-62 -403 b5 64 manufacturer ? s jedec id code mi cron 2c 65-71 manufacturer ? s jedec id code (continued) f f 72 manufacturing location 1 - 11 01 - 0b 73-90 module part number (ascii) x 91 pcb identification code 1 - 9 01 - 09 92 identification code (continued) 0 00 93 year of manufacture in bcd x 94 week of manufacture in bcd x 95-98 module serial number x 99-127 manufacturer-specific data (rsvd) ? note: 1. ? 1 ? / ? 0 ? : serial data, ? driven to high ? / ? driven to low. ? 2. x = variable data. 3. the jedec spd specification allows fast or slow slew rate values for these bytes. the worst-case (slow slew rate) value is represented here. systems requiring the fast slew rate setup and hold values are supported, provided the faster minimum slew rate is met.
16 16, 32 meg x 64 ddr sdram dimms micron technology, inc., reserves the right to change products or specifications without notice. dd8c16_32x64ag_preview.p65 ? pub. 3/02 ?2002, micron technology, inc. 128mb (x64) 184-pin ddr sdram dimms preview note: all dimensions in inches (millimeters) max or typical where noted. min 184-pin dimm 8000 s. federal way, p.o. box 6, boise, id 83707-0006, tel: 208-368-3900 e-mail: prodmktg@micron.com, internet: http://www.micron.com, customer comment line: 800-932-4992 micron is a registered trademark and the micron logo and m logo are trademarks of micron technology, inc. data sheet designation preview: this data sheet contains the present description of a products in definition with no formal design in progress. u1 u2 u3 u4 u6 u7 u8 u9 no components this side of module u10 1.255 (31.88) 1.245 (31.62) pin 1 .700 (17.78) typ. .098 (2.50) d (2x) .091 (2.30) typ. .250 (6.35) typ. 4.750 (120.65) .050 (1.27) typ. .091 (2.30) typ. .040 (1.02) typ. .079 (2.00) r (4x) .035 (0.90) r pin 92 front view back view .054 (1.37) .046 (1.17) 5.256 (133.50) 5.244 (133.20) 2.55 (64.77) 1.95 (49.53) pin 184 pin 93 .150 (3.80) .150 (3.80) typ. .394 (10.00) typ. .125 (3.18) max

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